characterization | Scholarship for Nigerians and Africans

PhD Position – Thermal Effects in 3D Integrated Circuits, France

The fellowship will be grated throughout the duration of the work, which will take place in a highly dynamic and international field in Grenoble (France).
The high requirements on today’s mobile systems push them beyond the limit of a simple communication tool, and make them reminiscent of a
global assistance terminal that includes entertainment, office and general services. This translates into a continuous increase in terms
of required computational performance. The scaling ability of complementary metal-oxide-semiconductor (CMOS) technology offers one
possible way to increase the system performance. However, it comes with a high cost in terms of fabrication complexity and power
efficiency. Another alternative that addresses these hurdles consists of vertically staking electronic chips on top of each other using
vertical connections (Fig. 1) called the through-silicon vias (TSV), thus increasing the computational performance, while using the same
system footprint.

Key competences:

– Knowledge in the field of classical thermal physics
– Understanding of solid-state physics and MOS transistors
– Ability to carry out physical modelling and numerical simulations
using a finite element simulator
– Ability to carry out electrical test and characterization and to
develop automated data input and processing tools
– Basic understanding of CMOS circuits and logic systems
– Ability to design basic logic circuits or ability to develop this competence
– Required team work within the frame of numerous collaborations with the involved teams
– Excellent time management skills
– Creativity, self-motivation, personal engagement
– Very good academic grade

Scholarship Application Deadline: Contact Employer, haykel.ben-jamaa-at-cea.fr

Further Scholarship Information and Application

PhD Position – Thermal Effects in 3D Integrated Circuits, France

The fellowship will be grated throughout the duration of the work, which will take place in a highly dynamic and international field in Grenoble (France).
The high requirements on today’s mobile systems push them beyond the limit of a simple communication tool, and make them reminiscent of a
global assistance terminal that includes entertainment, office and general services. This translates into a continuous increase in terms
of required computational performance. The scaling ability of complementary metal-oxide-semiconductor (CMOS) technology offers one
possible way to increase the system performance. However, it comes with a high cost in terms of fabrication complexity and power
efficiency. Another alternative that addresses these hurdles consists of vertically staking electronic chips on top of each other using
vertical connections (Fig. 1) called the through-silicon vias (TSV), thus increasing the computational performance, while using the same
system footprint.

Key competences:

– Knowledge in the field of classical thermal physics
– Understanding of solid-state physics and MOS transistors
– Ability to carry out physical modelling and numerical simulations
using a finite element simulator
– Ability to carry out electrical test and characterization and to
develop automated data input and processing tools
– Basic understanding of CMOS circuits and logic systems
– Ability to design basic logic circuits or ability to develop this competence
– Required team work within the frame of numerous collaborations with the involved teams
– Excellent time management skills
– Creativity, self-motivation, personal engagement
– Very good academic grade

Scholarship Application Deadline: Contact Employer, haykel.ben-jamaa-at-cea.fr

Further Scholarship Information and Application

Research Fellowship in the Department of Botany at Lucknow University, India

Applications are invited for the purely temporary position of a Research Fellow (JRF/SRF) in CSIR sponsored project entitled “Predicting ploidy response to body size and productivity in aromatic grasses: Histological, developmental and histochemical characterization of cell geometry in diploid vs. autopolyploid clones”, with the undersigned. Salary shall be commensurate with the prevailing rates for JRF / SRF as per CSIR rules. The position is co?terminus with the project and the person employed in the project shall have no claim to any University position, permanent or otherwise. Candidates should apply on plain paper clearly mentioning their educational qualifications and percentage obtained at graduate and post graduate level. There is no application fee. Performance at the interview and the academic qualifications of the candidates shall form the basis of selection. Applications are acceptable only as hardcopy and should be delivered in person to the PI (Seshu Lavania). Copies of all the relevant documents (proof of date of birth, marks sheets for B.Sc and M.Sc and NET / GATE result) must accompany the application. The original documents are required to be produced at the time of interview.
Eligibility: NET or GATE qualified candidates with M.Sc in Botany / Plant Science may apply. Students having qualified NET under the categories i) JRF and ii) Lecturership (NET) or those having qualified GATE shall be considered. Candidates possessing a sound background of Plant systematics and histological / histochemical techniques will be preferred.

Scholarship Application Deadline: 21 May 2011.

Further Scholarship Information and Application